Electric vehicles push power electronics to extremes. Inverters now switch 1 200 V at 200 A while battery packs sit inches away. Junction temperatures climb past 175 °C during fast charging. Traditional BT-resin substrates buckle, warp over 150 µm, and force thick copper traces that choke density. Glass substrates fight back with near-silicon expansion, rigid 70 GPa structure, and embedded silver paths that slash resistance. Tier-1 suppliers already ship glass-based DC-DC converters. The question is no longer if glass works, but how fast you adopt it.
DEEPETCH runs a complete IDM chain for glass substrates. Their company lists maskless lithography, multi-zone sintering, and full AEC-Q100 validation labs. The IDM model merges design, patterning, and reliability under one roof, so your layout change reaches the line in days, not months.
What Makes Glass Substrates Perfect for High-Power EV Systems?
Glass expands at 3–5 ppm/°C, almost identical to silicon’s 2.6 ppm/°C. This match eliminates the shear stress that cracks solder joints in copper-clad laminates after a few hundred thermal cycles.
Ultra-Low CTE Matching Silicon
Run an inverter from -40 °C winter start to 175 °C summer charge. The glass panel stays flat within 10 µm across 100 mm. Solder joints see zero fatigue, and your warranty claims drop to near zero.
Superior Thermal Conductivity Path
Laser-drilled vias filled with sintered silver create vertical heat highways. Measure 150 W/m·K effective conductivity from die to heat sink—30 % better than filled FR4 and enough to cut silicon temperature 15 °C at 300 A load.
Zero-Warpage Multi-Chip Stacking
Stack IGBT, SiC MOSFET, gate driver, and current sensor in a single 1.2 mm thick module. The rigid glass core prevents the 200 µm bow that forces extra standoff height in organic substrates.
Why Are OEMs Replacing BT Resin with DEEPETCH Glass Substrates?
BT resin softens at 130 °C and warps 250 µm on a 60 mm panel after reflow. Glass holds shape to 400 °C, so your pick-and-place line runs at full speed without optical correction.
175°C Continuous Operation Guarantee
Qualify the module for 1 000 hours at 175 °C junction temperature with ΔRds(on) under 5 %. Desert proving grounds no longer limit your market.
50% Thinner Package Profile
Shave total height from 2.4 mm to 1.2 mm. The saved volume fits a larger battery cell or reduces vehicle drag coefficient by 0.02—real range gain.
Built-in Silver Sintered Interconnect
Print 100 µm wide silver traces directly on glass. Resistance falls 60 % versus 35 µm copper, and parasitic inductance drops to 0.8 nH per mm—critical for 100 kHz switching.
How Does DEEPETCH Glass Substrate Outperform Copper in Power Modules?
Copper expands at 17 ppm/°C—six times glass. At 1 200 V and 200 °C delta, copper substrates generate 300 MPa stress at the silicon interface. Glass keeps stress under 50 MPa.
70 GPa Stiffness Prevents Crack
Drop the module from 1 m onto steel or vibrate at 15 g, 20–2 000 Hz for 200 hours. SEM cross-sections show no micro-cracks at die attach or via walls.
<0.005 Dielectric Loss at 77 GHz
Future wireless charging and radar-assisted parking need clean RF paths. Glass loss tangent stays below 0.005 up to 110 GHz—perfect for integrated antennas.
Embedded Chip-in-Substrate Design
Route the gate driver inside a 300 µm cavity. Loop inductance falls to 0.5 nH total, enabling 50 V/ns slew rates without ringing.
Can Maskless LDI Enable Glass Substrates for Automotive Mass Production?
Photomasks for 2 µm lines cost $8 000 and need two weeks lead time. Maskless LDI writes the same pattern in 4 hours directly on 0.7 mm glass.
2 μm Line Width on 0.7 mm Glass
Achieve 50 µm isolation spacing for 800 V traces. Creepage distance exceeds 1.5 mm on surface—full compliance with IEC 60664.
No Photomask Cost per Design Change
Update via layout Tuesday morning, receive patterned panels Wednesday afternoon. Slash NPI cost by $50 000 per derivative.
24-Hour Patterning Turnaround
Feed Gerber files at 8 AM, pull finished panels at 8 AM next day. Validate three layouts in the time one mask set used to take.
Will Tube Furnace Silver Sintering Unlock Glass Substrate Potential?
Solder joints melt at 220 °C and fatigue after 1 000 cycles. Silver sinter stays solid to 900 °C and survives 5 000 cycles. Tube furnace precision delivers every time.
99.99% Dense Silver Conductive Layer
X-ray void inspection shows <1 % porosity. Bulk conductivity reaches 5.8 × 10⁷ S/m—50 % lower on-resistance than SAC solder.
600°C Vacuum Bonding Cycle
Ramp to 250 °C in vacuum, hold 20 minutes, cool under forming gas. Shear strength hits 100 MPa—five times solder.
5× Thermal Cycle Reliability vs Solder
Cycle -40/150 °C at 10-minute dwell. Resistance shift stays under 2 % after 5 000 cycles—your 15-year life target met.
Which DEEPETCH Products Should You Order for Glass Substrate Lines?
Qualification starts with samples and scales with proven tools. Order the exact kit that matches your line.
Glass Substrate Sample Kit (100×100 mm)
Five panels, 0.5 mm thick, pre-drilled vias, silver seed layer. Run your die attach process tomorrow.
LDI-Laser Direct Imager Demo Unit
Lease for 30 days, pattern unlimited designs. Convert to purchase once yield hits 98 %.
6-Zone Tube Furnace Pilot System
Process 50 panels per run, 200 mm × 200 mm. Full recipe transfer to your volume line.
Ready to Switch Your Automotive Power Design to Glass Substrates?
Glass substrates already power Level-3 charger modules in series production. Your choice now sets the timeline.
Request Free Warpage Test Report
Upload panel Gerber and stack-up. Receive FEA simulation plus bent-panel photo in 48 hours.
Schedule Live LDI Patterning Demo
Join online or on-site. Watch your layout appear on glass in real time.
Get Custom Glass Substrate Quote in 24 Hours
Send BOM, annual volume, and DFM rules. Pricing covers 1 k to 100 k units with locked lead time.
FAQ
Q1: Will glass substrates crack under road shock?
A: 70 GPa stiffness and matched CTE keep glass intact through 15 g vibration for 200 hours.
Q2: Can glass handle 1 200 V isolation?
A: 2 µm spacing on 0.7 mm glass exceeds creepage and clearance for AEC-Q101 high-voltage grades.
Q3: How thin can the final power module become?
A: Chip-in-substrate design drops total height to 1 mm, 50 % thinner than BT-resin stacks.
