Silicon On Insulators (Soi)

• Material of SOI

SOI material consists of three layers:

1. Top silicon (TOP SILICON LAYER)

Monocrystalline silicon thin films, typically 50 NM to 2 ΜM thick, are used to manufacture active devices such as transistors and require high crystal quality and electrical uniformity

2. Insulation layer (BURIED OXIDE LAYER, BOX)

Silica (SIO₂) layers, typically 100-400NM thick, provide electrical isolation and suppress parasitic capacitance.

3. Backing layer (SUBSTRATE)

The body silicon (monocrystalline silicon) is about 500-700 ΜM thick and provides mechanical support and heat dissipation capability.

• Manufacturing process of SOI

1. SIMOX (SEPARATION BY IMPLANTATION OF OXYGEN) (Separation and injection of oxygen) method

High-dose oxygen ions (energy 100-200 KEV, dose 1×10¹⁸ IONS/CM²) are implanted into the silicon substrate to form a buried oxygen layer precursor. The implanted oxygen atoms react with silicon at high temperatures (annealing for several hours at 1300-1400℃) to form SIO₂ and release damage stress. The process is simple; surface damage layers are removed through chemical mechanical polishing (CMP), resulting in a smooth top silicon layer. Oxygen ion implantation is costly but suitable for small-scale production.

2. SMART CUT Method

By implanting hydrogen ions (dose 1×10¹⁶ IONS/CM²) into the donor silicon wafer to form an buried layer, bonding and heating the target silicon wafer cause the hydrogen bubbles to expand, leading to separation of the silicon wafer along the implanted layer. The thin top silicon layer is retained on the target substrate. The SOI structure is formed through ion implantation and stripping techniques. Finally, the top silicon layer is further polished and annealed to eliminate defects, transferring the top silicon layer onto the target silicon wafer. This method is low-cost and suitable for large-scale production, making it the current mainstream SOI manufacturing technique.

3. BOND AND ETCH-BACK (bonding and back etching) method

Two silicon wafers are bonded through a layer of silicon dioxide, and one of the wafers is thinned using chemical mechanical polishing (CMP). One of the wafers has a layer of silicon dioxide grown on its surface beforehand. Most of the material from one wafer is removed through grinding and etching, leaving a thin layer of silicon as the top silicon. The process is complex but allows for precise control over the thickness of the top silicon.

4. Epitaxial growth method

A single crystal silicon layer is grown on the insulating layer by epitaxial growth technology. It is suitable for special applications, such as thick film SOI.

• Material properties of SOI

1. Electrical properties

High resistivity: the resistivity of buried oxygen layer is>10¹⁴ Ω·CM, which effectively isolates leakage between devices.

Low parasitic capacitance: reduces the capacitance between the source/drain and the substrate, improving the switching speed (delay reduced by more than 30%).

Threshold voltage is adjustable: the device characteristics can be flexibly designed by adjusting the thickness and doping concentration of the top silicon layer.

2. Thermal performance

High temperature resistance: can withstand continuous operation above 300℃, suitable for automotive electronics, industrial control and other high temperature environment.

Thermal optimization: The thermal conductivity of the supporting substrate silicon (148 W/ (M·K)) is better than that of insulating materials such as glass.

3. Mechanical and chemical properties

High mechanical strength: The Young’s modulus of silicon (190 GPA) ensures the reliability of wafer processing.

Process compatibility: compatible with traditional CMOS process, no additional high temperature steps are required.

Radiation resistance: The insulation layer provides good radiation resistance and is suitable for aerospace applications.

Compatibility: Compatible with traditional CMOS process and easy to integrate.

• SOI’s industry applications

1. High voltage and power devices

IGBT and MOSFET: buried oxygen layer isolation for high voltage (>1200 V) and reduced on-state resistance.

Automotive electronics: used in engine control units (ECUs) and battery management systems (BMS), with tolerance to extreme temperatures of-40℃ to 150℃.

2. RF and microwave devices

Radio frequency front end (RF-SOI): Used for 5G millimeter wave RF switches (such as SKYWORKS’S SKY5® series), insertion loss <0.5 DB

5G chip: SOI’s low parasitic capacitance and high cutoff frequency (FT>200 GHZ) improve signal transmission efficiency.

Millimeter wave radar: used for 77 GHZ vehicle-mounted radar chip to reduce signal loss.

Low-power processors: IBM’s POWER server chips use SOI technology to improve energy efficiency by 40%

3. Sensor MEMS

Pressure sensor: the insulation of the buried oxygen layer is used to achieve high sensitivity and anti-interference ability.

Micro accelerometer: The mechanical stability of SOI supports high precision inertial measurement.

Gyro: SOI technology is used in MEMS gyroscopes to improve accuracy and stability

• SOI’s industry applications

1. High voltage and power devices

IGBT and MOSFET: buried oxygen layer isolation for high voltage (>1200 V) and reduced on-state resistance.

Automotive electronics: used in engine control units (ECUs) and battery management systems (BMS), with tolerance to extreme temperatures of-40℃ to 150℃.

2. RF and microwave devices

Radio frequency front end (RF-SOI): Used for 5G millimeter wave RF switches (such as SKYWORKS’S SKY5® series), insertion loss <0.5 DB

5G chip: SOI’s low parasitic capacitance and high cutoff frequency (FT>200 GHZ) improve signal transmission efficiency.

Millimeter wave radar: used for 77 GHZ vehicle-mounted radar chip to reduce signal loss.

Low-power processors: IBM’s POWER server chips use SOI technology to improve energy efficiency by 40%

3. Sensor MEMS

Pressure sensor: the insulation of the buried oxygen layer is used to achieve high sensitivity and anti-interference ability.

Micro accelerometer: The mechanical stability of SOI supports high precision inertial measurement.

Gyro: SOI technology is used in MEMS gyroscopes to improve accuracy and stability

4. Anti-radiation electronic equipment

Aerospace: The buried oxygen layer reduces the charge accumulation caused by ionizing radiation and improves the ability to resist single particle flip (SEU).

5. High performance integrated circuits

Microprocessors: SOI technology is used in high-performance microprocessors to improve speed and reduce power consumption.

Quantum bits: Spin quantum bits of silicon in SOI structure, with decoherence time extended to more than 1 second

• Technical indicators and advantages

1. Core physical properties

Electrical properties:

The parasitic capacitance is reduced by 60-70% (compared to bulk silicon), and the power consumption is reduced by 30-50%.

The anti-latch effect (LATCH-UP IMMUNITY) is suitable for high reliability scenarios.

Thermal properties:

The thermal conductivity of the oxygen-moisturized layer is low (SIO₂: 1.4 W/M·K), so the heat dissipation design needs to be optimized (integrated diamond heat dissipation layer).

mechanical behavior:

The radiation resistance is increased by more than 100 times (due to the insulation layer blocking charge accumulation), suitable for aerospace electronics.

2. Improved device performance

Speed and power consumption: Compared to bulk silicon, SOI devices have a lower subthreshold swing (<90 MV/DEC) and a reduction in leakage current of more than 90%.

Integrated density: The buried oxygen layer eliminates the latch effect and allows for smaller device spacing (e.g., below 28 NM nodes).

3. Special environmental adaptability

High temperature stability: electrical performance is maintained at 200℃, far exceeding the body silicon (about 150℃ limit).

Radiation resistance: when the buried oxygen layer thickness is greater than 100 NM, it can withstand the dose of 10⁶ RAD (SI).

4. Process advantages

Simplify the manufacturing process: reduce the cost by reducing the well injection and isolation oxidation steps.

3D integration potential: supports vertical stacking (such as SOI wafer bonding) to achieve high density packaging.

5. Technical advantages

• Power consumption and performance balance: achieve the combination of “high speed + low power consumption” by reducing leakage current and parasitic capacitance.
• Interference resistance: the insulation layer blocks substrate noise and improves the signal to noise ratio (SNR) of RF and analog circuits by 15 DB.
• Design flexibility: Supports partially depleted (PD-SOI) and fully depleted (FD-SOI) architectures to cover the entire process from micron to nanometer.
• System integration: compatible with CMOS process, can integrate optical, electrical and mechanical functions into a single chip (optical MEMS micro-mirror).

6. Comparative advantages of technical indicators

| metric                |SOI technology           | Traditional bulk silicon (BULK SI)

| leakage current              | Reduced by 90%           | higher

| Maximum operating frequency         | 300 GHZ+          | 100 GHZ

| Anti-single particle flip (SEU) | Very strong              | weak

| Manufacturing cost (300 MM) | $500-800/plate | $100-300/plate

• Future development trends

1. Cost bottleneck: The price of SOI wafer is 2-5 times that of bulk silicon, and the cost needs to be reduced through 12-inch mass production and technology iteration.
2. Heat dissipation optimization: Develop nano-heat dissipation structures (such as graphene channels) embedded in the oxygen layer to improve thermal management capability.
3. Expansion of emerging fields:

Flexible electronics: ultra-thin SOI layers are transferred to flexible substrates for wearable devices.

3D integration: The SOI interposer enables chip stacking to break the limits of Moore’s Law

Silicon on Insulator (SOI) stands out with its unique “silicon-insulator-silicon” structure, demonstrating irreplaceable advantages in low-power, high-frequency, and radiation-resistant scenarios. As FD-SOI technology advances to 3 NM nodes and silicon photonics and quantum computing converge, SOI will continue to drive innovation in high-performance semiconductor devices, becoming the core carrier for next-generation intelligent chips and heterogeneous integration.